`timescale 1ns / 100ps

module trigger_tb ();

    reg  clk;
    reg  rst_n;
    reg  start;
    wire trg;

    initial begin
        $dumpfile("./output/trigger.vcd");
        $dumpvars(0, u_trigger);

        clk = 0;
        rst_n = 1;
        #1; 
        rst_n = 0;
        #1; 
        rst_n = 1;
        #6;

        start = 1;
        #10;
        start = 0;

        #20;
        start = 1;
        #100;
        start = 0;

        $finish;
    end

    always #10 clk = ~clk;

    trigger u_trigger (
        .clk(clk),
        .rst_n(rst_n),
        .start(start),
        .trg(trg)
    );

endmodule